This invention relates generally to a circuit for generating a mode control signal, and more specifically to an integrated circuit package containing several megacells where the mode control signal is used to connect I/O signals and other signals of a megacell to the pins of the integrated circuit package.
Very large scale integration (VLSI) has high component (e.g., transistors, logic gates, etc.) densities in a single integrated circuit package. Typically, each package houses a complex device such as a central processing unit (CPU), interface adapter, memory, etc., which are modules used to build, for example, a dedicated computer system. Each package contains a die which is a semiconductor substrate upon which has been fabricated the transistors and other components of the device. Common methods of fabricating the die include chemical vapor deposition, ion implantation, and molecular beam epitaxy. Each of these methods uses some form of design definition of the interconnections and placement of components which make up the device.
These design definitions can exist physically, as in the case of a mask used in a photolithographic process, or the design definition may merely exist in a computerized database. All such design definitions will be referred to in this specification as megacells.
Over the years, manufacturers have cataloged a large library of megacells used to build devices which have been marketed. Recently, new technology has emerged which makes it possible to combine the dies generated by each mask onto a single large substrate, thereby providing that several previously discretely packaged dies can be combined into one integrated circuit package. In such a device comprising 2 or more dies on a single substrate, each die is then referred to as a megacell.
One form of this technology produces what are called application specific integrated circuits (ASICs), where a manufacturer will produce for a customer a single integrated circuit package designed to meet the customer's specific application. For example, a CPU, an interrupt controller and a peripheral interface adapter can be combined into one ASIC, thus achieving in one integrated circuit package what previously required three packages mounted on a circuit board including interconnecting metallized conductors and various support circuitry.
In an ASIC, the megacells are connected to each other as needed by conductors fabricated onto the single substrate. Additionally, "glue" logic is provided on the substrate to perform functions which were previously formed by small-scale or medium-scale discretely packaged integrated circuits. Thus, this technology provides a great savings in size, and other benefits such as lower power consumption.
However, a problem with ASIC technology is that it is difficult to independently test or exercise each of the megacells once the package has been assembled. It is desirable to be able to test each megacell independently since logically each megacell performs a well-defined function. Usually, testing software already exists for these megacells as each megacell has been previously manufactured and marketed as a discrete device. However, this testing software assumes that all of the input and output (I/O) signals to and from the megacell are available at package pins, this being the case when the megacell was discretely packaged. In an ASIC, though, many of a given megacell's I/O signals will not be available at the integrated circuit package pins because the megacell's I/O signals have been directly interconnected with other megacells on the substrate so in normal operation it is no longer necessary to provide those signals externally to the ASIC package.
Therefore, it is desirable to provide a means whereby an individual megacell's I/O signals will be made available at the pins of the ASIC so they may be accessed externally for testing purposes. This may mean that all of a megacell's I/O signals, or merely a subset of a megacell's I/O signals, need to be present at the ASIC's pins.
As many signals as are needed for complete testing of the megacell must be provided at pins. However, such pins are usually in short supply in a given integrated circuit package. In today's designs, many of the pins on a given integrated circuit package are already performing more than one function, and there are no spare pins. Also, this individual megacell testing will typically only be done at the time of manufacture, and it is undesirable to provide I/O signals at package pins which are not needed by the end user.
As used in this specification, "I/O signals," or merely, "signals," means any electrical connection to a device or megacell including power connections.
It is a primary object of the present invention to provide a means of switching megacell I/O signals to output pins on an integrated circuit package in order to individually test a megacell, wherein this means has no impact on the end use of the package.